EFTON P89LPC932A1 T89C51RD2 AT89C51RD2/ED2 P89C51RD2 (2nd generation - no H suffix) P89V51RD2 DS89C450(430,440) MSC1210
manufacturer Philips Temic (now Atmel) Atmel Philips Philips Dallas-Maxim Texas Instruments (Burr-Brown)
max.clock 12 MHz - 2clk mode 40 MHz in 12clk mode 20 MHz in 6clk (x2) mode 60 MHz / 40 MHz (*) in 12clk mode 30 MHz / 20 MHz(*) in 6clk (x12) mode (*) - @ full VDD range, incl.external code execution 33 MHz in 12clk mode 20 MHz in 6clk (x2) mode 40 MHz in 12clk mode 20 MHz in 6clk (x2) mode 33 MHz - 1clk mode 33 MHz - 4clk mode
x2 mode set N/A sw register, independent for core and peripherals sw register, independent for core and peripherals, core x2 bit loaded from hw register (HSB.X2) on reset sw register, independent for core and peripherals, core forced x2 mode when hw bit programmed (FX2) hw register, can be set by IAP/ISP, cleared only using parallel programmer N/A N/A
XRAM 512 B 1024 B 1792 B 768 B 768 B 1024 B 1024B (can be program memory)
EEPROM 512 B 2048 B 2048 B (ED2 only) no no no no
EEPROM endurance min. 100 k cycles 100 k cycles 100 k cycles N/A N/A N/A N/A
EEPROM retention ? ? ? N/A N/A N/A N/A
code FLASH (excluding boot area) 7.5 kB 63 kB 64 kB 64kB 64kB 64kB (430-16kB, 440-32kB) 4/8/16/32kB (suffixes Y2/Y3/Y4/Y5)
boot FLASH/ROM 0.5 kB FLASH continued (1E00h-1FFFh) 1kB FLASH continued 2kB ROM overlapped 1kB ROM overlapped 8kB FLASH overlapped (2kB - not user accessible) 2kB ROM non-overlapped
FLASH endurance 100 k cycles 100 k cycles 100 k cycles 10 k cycles 10 k cycles 20 k cycles min. 100 k, typ. 1000 k cycles
FLASH retention 10 years 10 years 10 years 10 years 100 years 100 years 100 years
FLASH programming time 2 ms 10 ms (including erase) 10 ms (including erase) 8 us ? 40 us 30-40 us
FLASH page erase time 2 ms 10 ms 10 ms 3 s ? 4 ms (min.) 10 ms
FLASH page size 64 B (1 kB sectors) 128 B (transparently bytewise programmable) 128 B (transparently bytewise programmable) 4 kB 128 B - 128 B
boot hw invocation 3 pulses of given duration on RESET /PSEN=0 & /EA=1 & ALE=1 /PSEN=0 & /EA=1 & ALE=1 /PSEN=0 & /EA=1 & ALE=1 successful autobaud within cca 400ms /PSEN=0 & /EA=0 & RST=1 (RST must remain active) /PSEN=0 & ALE=1
boot hw start address BOOTVEC*100h FC00h FC00h SBV*100h 0000h N/A 0000h while in bootloader mode, F800h in normal (user) mode
boot sw invocation BOOTSTAT.0=1 BSB>0 & BLJB=0 BSB>0 & BLJB=0 BSB>0 N/A N/A N/A
boot sw start address BOOTVEC*100h SBV*100h SBV*100h SBV*100h N/A N/A N/A
extras BOD, WDT, SPI, I2C extra 2 ports in PLCC68/VQFP64 clock prescaler, reset, WDT, keyboard interface, extra 2 ports in PLCC68/VQFP64, SPI
BOD, WDT,SPI BOD, WDT, 2xUART 8mux 24bit ADC, WDT, 2xUART, SPI, 16bit PWM, BOD
*** UART programming (ISP) ***
baudrate autobaud on “U” autobaud on “U” autobaud on “U” autobaud on “U” autobaud on “U” autobaud(on B?) - uses Timer1, UART0 autobaud on “CR”
command confirmation “.” “.” “.” “.” “.” G (Good), E (Error), also other responses ^C interrupts command processing “.” when uploading data “ok” or “x” when using erase or single-byte write command
               
program flash data :nnaaaa00dd..ddcc :nnaaaa00dd..ddcc - within 128-byte page :nnaaaa00dd..ddcc - within 128-byte page :nnaaaa00dd..ddcc - or - :nnaaaa07dd..ddcc :nnaaaa00dd..ddcc enter L command (or LB for load blind), then enter intelhex records: :nnaaaa00dd..ddcc enter L command, then enter intelhex records: :nnaaaa00dd..ddcc or use CWaaaadd to write 1 byte
EOF
:00xxxx01cc - ignored
:00xxxx01cc - ignored :00xxxx01cc - ignored after L command, this record terminates program upload :00xxxx01cc after L command, this record terminates program upload :00xxxx01cc
program other data

:nnaaaa07dd..ddcc - EEPROM

enter LX command for Load External data memory (MOVX), then enter intelhex records: :nnaaaa00dd..ddcc XWaaaadd - write 1 byte (dd) to external data memory (@ aaaa) XFaaaadd -write to data flash RWaadd - write to register (SFR) IWaadd - write to internal IRAM
full chip erase
:01xxxx0307cc (includes erasing SBV, BSB and SSB) :01xxxx0307cc (includes erasing/programming of SBV=FCh, BSB=FFh and SSB=FFh) :01xxxx0307cc (includes erasing SBV, BSB and SSB)
K command (erases also security block, option control register and bank-select bit) M0000 - erase flash
erase block :03xxxx0401aaaacc - erase sector = 1kB
:02xxxx030100cc (0000h-1FFFh) :02xxxx030120cc (2000h-3FFFh) :02xxxx030140cc (4000h-7FFFh) :02xxxx030180cc (8000h-BFFFh) :02xxxx0301C0cc (C000h-FFFFh) :02xxxx030100cc (0000h-1FFFh) :02xxxx030120cc (2000h-3FFFh) :02xxxx030140cc (4000h-7FFFh) :02xxxx030180cc (8000h-BFFFh) :02xxxx0301C0cc (C000h-FFFFh) :01xxxx0301cc (erase Block0 = user FLASH)
CPnnnn - erase 128-byte page containing the nnnn address XPnnnn - erase data flash page
erase sector :03xxxx0400aaaacc - erase page = 64 B

:02xxxx030Caacc (aa00h-aaFFh) sector = 4kB :03xxxx0308aaaacc sector = 128 B

hardware reset :00xxxx08cc
:02xxxx030300cc
:00xxxx0Bcc (resets to user FLASH) issuing break character restarts bootloader
erase/reset boot vector and status byte
:02xxxx030400cc - SBV=FCh, BSB=FFh :02xxxx030400cc :02xxxx030400cc :00xxxx07cc (reset serial number, incl. erase user FLASH, clear SoftICE mode)
M8000 - erase configuration flash
program software security bits (SSB) :02xxxx02ssddcc ss - 08h,09h,...,0Fh for Security Byte of sector 0,1,...,7 dd - data :02xxxx030500cc (Level2 - inhibit FLASH write) :02xxxx030501cc (Level3 - inhibit FLASH verify) :02xxxx030502cc - (disable external memory - bit ignored) :02xxxx030500cc - bit1 :02xxxx030501cc - bit2 :02xxxx030500cc (inhibit FLASH write) :02xxxx030501cc (inhibit FLASH verify) :02xxxx030502cc - (disable external memory) :02xxxx030501cc (only one security bit - inhibits FLASH access from parallel programmer)

program status byte (BSB) :02xxxx0203ddcc :03xxxx030600ddcc :03xxxx030600ddcc :03xxxx030600ddcc


program boot vector (SBV) :02xxxx0202ddcc :03xxxx030601ddcc :03xxxx030601ddcc :03xxxx030601ddcc


write serial number



:nnxxxx09ss...sscc write encryption vector: enter LE then enter intelhex records: :nnaaaa00dd..ddcc
program BLJB fuse

:03xxxx030A04ddcc



program X2 fuse (FX2)

:03xxxx030A08ddcc :03xxxx03060280cc :02xxxx030505cc

write other flags :02xxxx0200ddcc - UCFG1


:00xxxx02cc set SoftICE mode, will erase user FLASH and serial number

display FLASH data :00xxxx06cc - read global CRC :01xxxx05aacc - read sector CRC :05xxxx04sssseeee00cc (needs extra byte to start) :05xxxx04sssseeee00cc (needs extra byte to start) :05xxxx04sssseeee00cc (needs extra byte to start) :05xxxx04sssseeee00cc (needs extra byte to start) D [bbbb[eeee]] V for verify (works similar to L) CRaaaa - reads 16 byte from flash address aaaa
blank check
:05xxxx04sssseeee01cc :05xxxx04sssseeee01cc
:05xxxx04sssseeee01cc

display other data

:05xxxx04sssseeee02cc - EEPROM

DX [bbbb[eeee]] - display external data memory VX for verify (works similar to LX) XRaaaa - read 16 byte from external data memory address aaaa RRaa - read from register (SFR) IRaa - read from internal IRAM
read manufacturer ID :01xxxx0310cc - 15h :02xxxx050000cc - 58h :02xxxx050000cc - 58h :02xxxx050000cc - 15h :02xxxx050000cc - BFh

read family code (ID #1) :01xxxx0311cc - DDh :02xxxx050001cc - D7h :02xxxx050001cc - D7h :02xxxx050001cc - C2h :02xxxx050001cc - 91h

read memory size and type (ID #2) :01xxxx0312cc - 1Fh :02xxxx050002cc - FCh :02xxxx050002cc - ECh :02xxxx050002cc


read product name and revision (ID #3)
:02xxxx050003cc - FFh :02xxxx050003cc - EFh



read software security bits (SSB) :01xxxx03sscc ss - 08h,09h,...,0Fh for Security Byte of sector 0,1,...,7 :02xxxx050700cc :02xxxx050700cc :02xxxx050700cc :02xxxx050700cc (incl. x2 bit) R - Displays the values of the lock bits LB, option control reg. OCR,
read status byte (BSB) :01xxxx0303cc :02xxxx050701cc :02xxxx050701cc :02xxxx050701cc
address control reg. ACON,
read boot vector (SBV) :01xxxx0302cc :02xxxx050702cc :02xxxx050702cc :02xxxx050702cc
clock control reg. CKCON,
display serial number



:00xxxx0Acc power management reg. PMR,
read hardware security byte (HSB) :01xxxx0300cc - read UCFG1 :02xxxx050703cc :02xxxx050B00cc

Ports 0, 1, 2, 3, flash control reg. FCNTL. Faa - read 16 byte from configuration flash
read FX2 bit


:02xxxx050003cc


read extra byte

:02xxxx050706cc



read bootloader version :00xxxx01cc - read version ID (?) :02xxxx050800cc :02xxxx050F00cc :02xxxx050080cc :02xxxx050002cc
displays version after autobaud
read device boot ID1

:02xxxx050E00cc



read device boot ID2

:02xxxx050E01cc



direct load of baudrate :02xxxx07ddddcc

:02xxxx06ddddcc :02xxxx06ddddcc

miscellaneous
specify frequency :01xxxx02ddcc - ignored (was used on P89C51RD2Hxx chips)

unlock - verify serial number :nnxxxx08ss...sscc B - return CRC-16 of bootROM (always 0000h) C (CX) [bbbb[eeee]] - return CRC of flash (external data memory) VE - verify encryption vector (works similar to LE) before programming set up USEC, MSECL and MSECH registers (using RW command)!








*** self-programming (IAP) ***
boot/IAP memory enable N/A N/A ENBOOT=AUXR1.5=A2h.5 = 1 ENBOOT=AUXR1.5=A2h.5 = 1 SWR,BSEL=FCF.1,0=B1h.1,0=0,0 N/A EBR=HCR0.4=1 (set in config.flash when programming)
boot/IAP memory area FF00h-FEFFh (IAP) FC00h-FFFFh F800h-FFFFh FC00h-FFFFh 0000h-1FFFh N/A F800h-FFFFh during user mode
IAP entry address FF03h (prior each erase or write IAP call, 96h into IRAM FFh must be written) FFF0h FFF0h FFF0h 1FF0h write command to FCNTL:D5h write address/data to FDATA:D6h








program data byte
R1=02h ACC=programmed byte DPTR=target address returns 00h in ACC if pass ??? R0=osc.freq. R1=02h or 82h (WDT) ACC=programmed byte DPTR=target address returns 00h in ACC if pass R1=02h ACC=programmed byte DPTR=target address returns 00h in ACC if pass xxxx1011 to FCNTL + upper address + lower address + data byte to FDATA Write_flash - FFD9h - writes a byte to flash selected (code/data) by MXWS (see MWS SFR) bit DPTR-address, A-data
program data page/block ACC=00h R3=number of bytes R4:R5=high:low address R7=pointer to data in RAM F1 (PSW.1) = 0 - data in IRAM; 1 - data in XRAM if error, returns carry set and error status in R7 R1=09h DPTR0=target address DPTR1=source address ACC=number of bytes (target must remain in 128 byte page) returns 00h in ACC if pass R1=09h DPTR0=target address DPTR1=source address ACC=number of bytes (target must remain in 128 byte page) returns 00h in ACC if pass R0=osc.freq. R1=0Dh or 8Dh (WDT) DPTR=address (0001h-FFFFh) ???

Write_flash_byte - FFDDh - the same function, except address is in R7:R6 and data in R5 Write_flash_chk - FFDBh - the same function, but reads back an checks the byte; needs also R3 - 0 for code memory, 1 for data memory; returns R7=0 if success
erase block ACC=04h R4:R5=high:low address R7=01h - erase 1kB sector if error, returns CS + status in R7 (no need; automatic transparent erasure when programming) R1=01h DPTR=aaxxh (aa=00h,20h,40h,???) R0=osc.freq. R1=01h or 81h (WDT) DPTR=aaxxh (aa=00h,20h,40h,80h,C0h) R1=01h (erases whole user Flash) xxxx1110 to FCNTL (erases whole upper half of FLASH) Page_erase - FFD7h - erase 128byte page R6-high address, R7-low address, R3-0 for code memory, 1 for data memory; returns 0 in R7 on success
erase small block ACC=04h R4:R5=high:low address R7=00h - erase 64 B page if error, returns CS + status in R7

R0=osc.freq. R1=0Ch or 8Ch (WDT) DPTR=aaxxh (aa=00h,10h,20h,...,F0h) R1=08h - erase 128 byte sector DPTR=address

erase boot vector and status byte
R1=04h DPTR=00xxh ??? R0=osc.freq. R1=04h or 84h (WDT) DPTR=00xxh
xxxx1100 to FCNTL - erases option control register xxxx1101 to FCNTL - erases security block (incl. lockbits)
program software security bits (SSB) ACC=02h R7=08h..0Fh - security byte of sector 0..7 R5=data to write if error, returns CS + status in R7 R1=05h DPTR=0000h - program bit 1 DPTR=0001h - program bit 2 DPTR=0010h - clear bit 1 DPTR=0011h - clear bit 2 R1=05h DPTR=0000h (SSB Level1) DPTR=0001h (SSB Level2) DPTR=0010h (SSB Level0) DPTR=0011h (SSB Level1) R0=osc.freq. R1=05h or 85h (WDT) DPTR=0000h - program bit 1 DPTR=0001h - program bit 2 DPTR=0002h - program bit 3 R1=05h DPL=00h - security bit xxxx1010 to FCNTL + address in security block + data byte to FDATA
program boot status byte (BSB) ACC=02h R7=03h R5=data to write if error, returns CS + status in R7 R1=06h DPTR=0000h ACC=BSB R1=06h DPTR=0000h ACC=BSB R0=osc.freq. R1=06h or 86h (WDT) DPTR=0000h ACC=BSB


program boot vector (SBV) ACC=02h R7=02h R5=data to write if error, returns CS + status in R7 R1=06h DPTR=0001h ACC=SBV R1=06h DPTR=0001h ACC=SBV R0=osc.freq. R1=06h or 86h (WDT) DPTR=0001h ACC=SBV


program X2 fuse (FX2) ACC=02h R7=00h - program UCFG1 R5=data to write if error, returns CS + status in R7
R1=0Ah DPTR=0008h ACC=fuse value (00h or 01h) R0=osc.freq. R1=06h or 86h (WDT) DPTR=0002h ACC=80h R1=05h DPL=05h - Double clock xxxx1001 to FCNTL + data byte to write to the option control register
program BLJB fuse

R1=0Ah DPTR=0004h ACC=fuse value (00h or 01h)



read FLASH data ACC=07h R4:R5=high:low address returns data in R7 R1=03h DPTR=address returns data in ACC ??? R0=osc.freq. R1=03h or 83h (WDT) DPTR=address returns data in ACC R1=03h DPTR=address returns data in ACC xxxx0011 to FCNTL + lower address, upper address to FDATA - returns content of upper half of FLASH in FDATA x_c_read - FFE1h - reads a byte from program or data flash R6 - high address, R7 - low address, R3 - 0 for code memory, 1 for data memory; returns in R7
read FLASH data block ACC=05h - read sector CRC R7=sector address if no error, returns CRC in R4:R5:R6:R7 (R4-MSB) if error, returns CS + status in R7

R0=osc.freq. R1=0Eh or 8Eh (WDT) DPTR=address (0001h-FFFFh) ??? returns data in ACC
xxxx0000 to FCNTL sets to normal read mode (upper half of FLASH can be read and executed from)
read IDs ACC=06h - read global CRC if no error, returns CRC in R4:R5:R6:R7 (R4-MSB) if error, returns CS + status in R7 R1=00h DPTR=0000h - manufacturer ID DPTR=0001h - device ID1 DPTR=0002h - device ID2 DPTR=0003h - device ID3 returns in ACC R1=00h DPTR=0000h - manufacturer ID DPTR=0001h - device ID1 DPTR=0002h - device ID2 DPTR=0003h - device ID3 returns in ACC R0=osc.freq. R1=00h or 80h (WDT) DPTR=0000h - manufacturer ID DPTR=0001h - device ID1 DPTR=0002h - device ID2 DPTR=0003h - device ID3 returns in ACC R1=00h DPTR=0000h - manufacturer ID DPTR=0001h - device ID1 returns in ACC
read bootloader configuration bytes ACC=03h R7=00h - UCFG1 R7=02h - BOOTVEC R7=03h - BOOTSTAT R7=08h..0Fh - security byte of sector 0..7 if no error, returns data in R7 if error, returns CS + status in R7 R1=07h DPTR=0000h - SSB DPTR=0001h - BSB DPTR=0002h - SBV returns in ACC R1=07h DPTR=0000h - SSB DPTR=0001h - BSB DPTR=0002h - SBV returns in ACC R0=osc.freq. R1=07h or 87h (WDT) DPTR=0000h - SSB DPTR=0001h - BSB DPTR=0002h - SBV DPTR=0003h - config byte ??? returns in ACC R1=07h returns in ACC: ACC.0-double clock ACC.2-security bit ACC.4-serial number match status ACC.5-SoftICE status xxxx0001 to FCNTL - returns content of option control register in FDATA Faddr_data_read - FFDFh - reads a byte from configuration flash R7 - address; returns in R7
read hardware security bits (HW)
R1=07h DPTR=0003h returns in ACC R1=0Bh returns in ACC

xxxx0010 to FCNTL + security block address to FDATA - returns content of sec. block in FDATA
read bootloader version R1=00h DPTR=0002h returns in ACC R1=08h returns in ACC R1=0Fh returns in ACC R0=osc.freq. R1=00h or 80h (WDT) DPTR=0080h returns in ACC R1=00h DPTR=0002h returns in ACC

read boot ID ACC=01h returns version in R7
R1=0Eh DPTR=0000h ID1, 0001h ID2 returns in ACC



reset




xxxx1111 to FCNTL

Original excel table can be found here.