STM32 gotchas
100. In lower-end 'F0xx, GPIOC/GPIOD don't have AFR[2] registers

In STM32 (except the ancient 'F1 family), the individual peripherals are assigned pins through a sparse matrix in the GPIO module. To assign a pin to a peripheral, first pin has to be set to Alternate Function (AF) in its respective GPIOx_MODER field, and then the individual peripheral is selected by setting its assigned value in one of the GPIOx_AFR[2] registers (sometimes marked also as AFRL and AFRH).

In the lower-end STM32F0xx families ('F031, 'F042, 'F051, and the "value-line" derivatives of these, i.e. 'F030x4/6/8 and 'F070x6), in GPIOC and GPIOD, there is only one or no AF per pin. So, ST decided simply to omit the AFR[] registers from GPIOC and GPIOD.

This is properly documented in the initial section of the GPIO chapter in RM0090/RM0360, although it is formulated "inversely" (i.e. it says, that only GPIOA and GPIOB have the AFR registers).

There are also no Alternate functions tables in the respective datasheets for GPIOC and GPIOD.