There are two bit-banded areas in mcus based on the Cortex-M3/M4 processors - one intended to map a portion of SRAM, and onther intended to map peripherals. In STM32, connection to most peripherals is implemented through one or more "secondary/slower" APB bus connected through a bridge to an AHB bus within the bus matrix, and it's these APB buses which are mapped into the peripheral bit-banded area.

In STM32F1xx, GPIO was connected to such APB bus, so bits within its registers were bit-addressable. However, in all subsequent STM32 based on Cortex-M3/M4 (i.e. 'L1/'F2/'F4/'F3/'L4/'G4), GPIO resides on one of the AHB buses, presumably to allow faster access to them. As this AHB bus in all mentioned models is outside of the bit-banding areas, there is no bit-banding access to GPIO registers.

For the vast majority of applications this does not matter, as the most used GPIO register which requires atomic access is the output register, GPIOx_ODR; and for that, atomic writes are provided inside the GPIO module through the GPIOx_BSRR register (and in some cases, the mostly redundant GPIOx_BRR register). However, in some applications, atomic write into other GPIO registers would be benefitial, too. As this is unavailable through hardware (bit-banding), applications must apply the usual care, when accessing GPIO registers both from "main" and "interrupt".