ST has a good habit of locating the HSE oscillator pins onto PF0 and PF1, and the LSE oscillator pins onto PC14 and PC15, in all STM32 families. This goes that far, that GPIOF is present in the smallest STM32 models such as the 'F0, 'L0 and 'G0, which may even not have GPIOD and GPIOE.
However, if HSE is switched on in RCC (by setting RCC_CR.HSEON or similar), PF0 and PF1 cease to be controlled by GPIO. Most commonly a crystal (together with loading capacitors) is then connected between these two pins.
Sometimes an external clock source is used, in which case it is connected to OSC_IN = PF0, and RCC_CR.HSEBYP is set. In this case, the OSC_OUT = PF1 pin behaves differently in various families - in some families (e.g. 'F3 or 'G0) it is freed up and can be used as GPIO; in others (e.g. 'F4 or 'L0), the RM requires them to be left Hi-Z. So, availability of PF1 with external HSE clock source has to be checked for each family/model individually.
This is very similar for PC14 and PC15. Again, they are overriden by enabling LSE in RCC_BDCR.LSEON (RCC_CSR.LSEON in 'L0, which has no backup-domain so no Backup-Domain Control Register, BDCR); and again, in case of using external 32.768kHz clock source, in some families with setting of LSEBYP bit the OSC32_OUT = PC15 is freed up to be used as GPIO, and in other it has to be left Hi-Z.
Besides of that, if used as GPIO, PC14 and PC15 are in the low-power or VBAT-power-domain, so they usually have lowered drive capability as compared to other GPIO pins.