The STM32F723 (and it's "value" counterpart, the 'F730, but only in the 144- and 176-pin packages), has a built-in High-Speed USB PHY, connected to the OTG_HS module internally.

This PHY needs 60MHz and 480MHz clocks, which it generates internally directly from HSE. Unfortunately, this fact is not described in the dedicated USBPHYC chapter in RM0431 as it ought to be (instead, this chapter confusingly states both in narrative and in the schematic diagram, that only APB clock PCLK2 is connected to it). The real connection from HSE to the USB PHY's internal PLLs is depicted on the Clock tree diagram in RCC chapter.

As the USBPHYC_PLL1.PLLSEL description states, there's only a selected set of HSE frequencies from which the PHY's PLLs can generate the required 60MHz/480MHz clocks: 12MHz, 12.5MHz, 16MHz, 24MHz and 25MHz.

This means, that using the 8MHz crystal which is so widely used on ST's devboards won't allow to use the internal HS USB PHY in the 'F723. This same limitation together with bad design decisions also resulted in the STLink3 not being able to supply stable 8MHz clock to its connected target STM32.