In STM32F1xx family, there is no GPIO AF matrix as in other STM32 families. Instead, the mapping of peripherals to individual pins is more-less fixed. However, some peripherals have a limited flexibility in that their internal IO pads can be remapped to a different set of pins than is the default mapping. This is accomplished by writing to the respective bit-field in AFIO_MAPR register2.
Besides these remaps, AFIO_MAPR contains also the SWJ_CFG field intended to remap pins to the JTAG/SWD debug interface. Surprisignly, these SWJ_CFG bits are write-only and read as zero. This means, that any read-modify-write (RMW) operation on any other field in AFIO_MAPR writes all SWJ_CFG bits to zero, and thus remaps all JTAG/SWD pins to their debug function.
As bit-banding is by hardware converted to RMW, this problem occurs also if the periphepral remap bits are adjusted using bit-banding.
Solution is, that each time AFIO_MAPR register is to be written, the SWJ_CFG field has to be explicitly set to the bit combination required by the user for the affected pins to work as intended.
This has been brought up here and subsequently implemented by ST in Cube.
1. This problem pertains to PA13/PA14, too, as they are also part of SWD/JTAG interface remapped by AFIO_MAPR.SWJ_CFG, but this is less likely to be observed as those pins are usually dedicated to SWD debugging/programming.