In various STM32 families, there are two1 types of DMA: single-port and dual-port. Here, we are not going to discuss all the differences between these two types - which there are quite a few - only a confusing numbering issue.
Both DMA types consist of several (6-8) transfer elements and common steering logic. Each transfer element consists of holding register or FIFO for transferred data, source/destination address register and number-of-transfer register, and logic to load/increment these registers when a request (trigger) arrives for this transfer element. The common logic provides access to external bus/buses through which DMA reads/writes data, and arbitrate between transfer elements in case of simultaneous requests.
In single-port DMA, transfer elements are called Channels and they are numbered starting at 1. Individual requests from several periferals for one transfer element are either simply ORed together (where it's the user's responsibility to enable DMA only in one of the peripherals), or there is a multiplexer controlled by a separate register in the DMA.
In dual-port DMA, transfer elements are called Streams and they are numbered starting at 0. Requests to one stream are selected using a multiplexer, which is controlled by a field in the given stream's control register. Confusingly enough, individual requests are called channels...
Starting from the 'L4+ family, a new feature appered: the DMAMUX unit, which is in fact a DMA request multiplexing matrix with some additional functions such as synchronization and repetitions. The nature of matrix means, that each of the DMA transfer elements can be triggered by any of the dozens of available requests, so there is no more limitation of conflicting requests in one DMA transfer element.
The output side of DMAMUX consists of channels, with one channel for each DMA transfer element. However, DMAMUX channels are numbered starting at 0.
As most of the models with DMAMUX have the single-channel DMA, there is a confusing mapping from DMAMUX channels to DMA channels: DMAMUX ch0 triggers DMA ch1, DMAMUX ch1 triggers DMA ch2, etc.
There are STM32 models with DMAMUX and two DMA ('L4+ and 'G4). The channels of single DMAMUX are then split to serve the two DMAs. The DMAMUX channel numbering is continuous, so it depends on number of channels in the DMAs in individual models, how exactly the mapping splits. For example, in 'L4R5, DMAMUX channels 0-6 trigger DMA1 channels 1-7 and DMAMUX channels 7-13 are connected to DMA2 channels 1-7.
The 'H7 comes with an added bonus, as it contains both single- and dual-port DMA (plus the MDMA mentioned in footnote). It has two DMAMUX units - DMAMUX1 serves the dual-port DMA1 and DMA2, where DMAMUX1 channels 0-7 trigger DMA1 streams 0-7 (making it the only case where the numbering matches) and DMAMUX1 channels 8-15 trigger DMA2 streams 0-7; whereas DMAMUX2 serves the single-port BDMA, DMAMUX2 channels 0-7 triggering BDMA channels 1-8.