One of the central features of STM32 timers is the Update Event. This is basically the moment, when the timer's counter overflows. This event is then used to update all preloaded registers, resulting in a well-defined synchronous operation of all channels and other features of the timer.
However, in some "better" timers, the Update Event does not necessarily happen at every overflow of the counter. These have an additional register, Repetition Count Register - TIMx_RCR, and if this is set to nonzero, the Update Event occurs at every (TIMx_RCR + 1)-th overflow of the counter.
TIMx_RCR in itself is again a "holding" register, so its value is always what was written to it by the user (or the reset value which is 0). It is loaded into the actual repetition downcounter (which is internal and not user accessible) upon each Update Event, making it effectively unconditionally preloaded.
TIMx_RCR is present only in those timers which have channels with complementary output - TIM1, TIM8, TIM20 called collectively Advanced Timers, and TIM15, TIM16, TIM17. Of course, not all of these timers are present in all STM32 families/models, AN4013 gives a good overview of the available options.
As most STM32 timers (and their counting-related registers) are 16-bit, it may come as a surprise to learn that in many STM32, TIMx_RCR is only 8-bit wide.
In the 'F3, 'F7, 'G0, 'G4, 'H7, 'L4 and 'L5 families, TIM1, TIM8 and TIM20 (where available) do have 16-bit wide TIMx_RCR. However, even in those families, TIMx_RCR in TIM15, TIM16, TIM17 is still only 8-bit wide.