Timers in STM32 have several quite poorly described features. One of them is the TGI signal, which can only be seen on the timer block diagram at the beginning of timer chapter in RM. This signal stems from the TRGI input, and triggers interrupt and/or DMA transfer, pending TIMx_DIER.TIE/TDE being set, respectively.

Source of TRGI is selected by TIMx_SMCR.TS bitfield. It can be one of four internal sources (or more in newer STM32 families), which are connected to the TRGO outputs from other timers, thus forming inter-timer interconnection. TRGI can come also from external sources - TIMx_CH1/CH2 or TIMx_ETR pins.

Primary purpose of TRGI is not to trigger interrupt/DMA, but to control the counter's clock logic (called slave-mode controller). The exact behaviour of this is selected by TIMx_SMCR.SMS bitfield, causing TRGI e.g. to reset the counter, one-time enable clock, or gate the clock.

It may appear that once TRGI source is set, selection of TRGI's action in slave-mode controller should not interfere with the TRGI‑triggered interrupt or DMA. However, from experimentation it appears, that for the TGI interrupt/DMA to work, TIMx_SMCR.SMS should be set to nonzero value.