STM32 gotchas
174. Anecdotes about missing VDDx

Most of the STM32 models have multiple VDD and VSS (GND) pins. Besides the basic "digital" VDD/VSS, there are also "specialized" VDDx (and sometimes VDDx/VSSx pairs), such as the analog VDDA/VSSA (and although not supply, VREF+/VREF- pins partially belong to this group, too); VBAT for battery-backup (mostly for RTC but also BKPSRAM where available); VDDUSB for, well, USB; VDDIO2 for a couple of GPIO pins; VDDDSI/VDDSD/VDDSDMMC/VDDPHYHS for the MIPI/DSI display interface, Sigma-Delta converter (unique to STM32F373), SD/MMC unit, and internal USB High-Speed PHY (unique to STM32F723 and its "value-line" counterpart), respectively.

In the vast majority of cases, these pins should not be left unconnected, even if the related functionality is not explicitly used. Generally, all VSS/ground pins should be connected to a common ground potential; most of the "specialized" VDDx pins, if unused, can be tied to the "basic digital" VDD. The datasheet is always the definitive guide how to treat these pins.

If used, some of the "special" voltage domains are behind an isolation switch, which has to be switched on by software. VBAT-powered domain is behind a switch which is controlled by a circuitry related to brown-out and power-on-reset; although the backup SRAM if present, is powered from an internal low-power regulator which has an additional dedicated switch.

In any case, the "special" voltages have to be present and of required level, on the given VDDx pins, should the related functionality be used. While this sounds self-evident, if the related VDDx is inadvertently absent, the actual symptoms may be quite surprising. Following are two anecdotes resulting from such omission.

User wynandsp reported an interesting problem, where the USB D+ pin upon enabling the internal 1k5 pullup to indicate Full-Speed Device, generated short cca 10μs pulses every cca 450μs.

It turned out that by omission, power on VDDUSB was missing, only a 100nF capacitor was connected to this pin. While one would expect an entirely non-functioning PHY in this case, or a low-voltage but steady output level resulting from internal leakages, the pulsed output was genuinely confusing.

During hardware shakedown, an STM32F407-based design with VBAT connected to a CR2032-type coin cell exhibited confusing symptoms after a power cycle, akin to incomplete reset. Additionally, time in RTC was lagging a couple of seconds after each power cycle.

Investigation revealed, that a HF-choke through which VDDA was connected to VDD, had been removed in a previous test, and by mistake it had not been soldered back in place before the next tests. During powerdown, voltage on VDDA did not follow VDD but was kept relatively high thanks to its decoupling capacitor, thus the brownout-poweron reset circuitry did not engage and the internal VBAT-domain switch remained improperly switched to the powered-down VDD domain. As a consequence, the whole digital part of the mcu, and parasitically also part of the external circuitry; were supplied from a rapidly dying coin cell, and the incomplete power cycle on VDDA subsequently resulted in improper power-on reset.