The SPI/I2S unit in the 'H7 family is a significantly more complex implementation than the SPI/(I2S) modules in other STM32 families. This complexity results in arguable benefits, but also in surprising behaviour in certain corner cases.

One of these surprises, as experienced by user Alefal and explained by user LCE is, that when I2S/SPI SPI2S_RXDR register is read out (either by processor or by DMA) using a narrower data width than the module is configured for (in SPI_CFG1.DSIZE for SPI mode, or in SPI_I2SCFGR.DATLEN for I2S mode), zeros are read out. In the mentioned case this occured, when the module was configured for 24-bit I2S frames but the DMA reading out the data was configured for 16-bit (halfword) transfers.

This behaviour is documented in the relevant RMs as an inconspicuous remark in the rather lengthy narrative related to the RxFIFO:

The FIFO data access less than the configured data size is forbidden. One complete data frame has to be always accessed at minimum.