In several STM32, there is a choice of clocks available for I2S, including a dedicated input from external pin through the GPIO matrix, and a dedicated PLL unit. There is a multiplexer in RCC to choose between them, controlled by I2SxSRC fields in RCC_DCKCFGR register. The "x" in name of the field (and thus naming of respective clock signal as "I2Sx clock") is bound to the APBx bus, on which the SPI/I2S unit(s) fed by this clock reside.

In 'F446 and 'F413/'F423 it so happens, that SPI1/I2S1 is on APB2, and SPI2/I2S2 is on APB1 (there are more SPI/I2S units in either of these STM32, though). Thus, I2S1 is fed by "I2S2 clock" and I2S2 is fed by "I2S1 clock".

This can get very confusing...