STM32 gotchas
189. ... or the clock is enabled by default...

In various STM32 models/families, there are peripherals which do have a clock enable bit, but it is set by default.

As most enable bits are clear after reset, bits which are enabled by default may cause confusing behaviour if an unaware user clears the whole RCC_AxBxENR register containing such bit, e.g. when trying to restore reset state, typically when transitioning from bootloader to application.

Examples of such bits include:

There is also a confusing exception (sort of): in the 'F1, 'F0 and 'F3 families, there are FLITFEN and SRAMEN enable bits for the FLASH interface and SRAM; and indeed, they are set by default. However, clearing these bits wouldn't switch off the FLASH interface and SRAM during Run mode, as they are relevant only during Sleep mode1.

1. Contrary to other STM32 families, the 'F1/'F0/'F3 families do not have dedicated low-power clock enable registers.