In various STM32 models/families, there are peripherals which do have a clock enable bit, but it is set by default.

As most enable bits are clear after reset, bits which are enabled by default may cause confusing behaviour if an unaware user clears the whole RCC_AxBxENR register containing such bit, e.g. when trying to restore reset state, typically when transitioning from bootloader to application.

Examples of such bits include:

• CCMDATARAMEN, enable bit for the CCM RAM in 'F4
• DTCMRAMEN, enable bit for the DTCM RAM in 'F7
• FLASHEN, enable bit for the FLASH registers in 'L4/'L5/'G0/'G4 - this bit can't be cleared unless FLASH itself is powered down by setting FLASH_ACR.RUN_PD. Confusingly, the same bit in 'L1 is called FLITFEN; and in 'L0 it's called MIFEN.
• RTCAPBEN, enable bit for interface between RTC and APB (bus matrix) - this bit is present in all STM32 models, and it is also enabled only in some STM32 models by default

There is also a confusing exception (sort of): in the 'F1, 'F0 and 'F3 families, there are FLITFEN and SRAMEN enable bits for the FLASH interface and SRAM; and indeed, they are set by default. However, clearing these bits wouldn't switch off the FLASH interface and SRAM during Run mode, as they are relevant only during Sleep mode¹.