In higher-end and newer STM32 RCC, PLL units have usually 3 outputs, marked P, Q and R, which divide down output of the same oscillator (VCO) by 3 different ratios, before they are used for various purposes (system clock, 48MHz USB clock, audio/I2S clock, independent clock for other peripherals etc.) in the rest of given STM32.
In newer STM32 families ('G0,'G4,'L4,'L5), besides a register bit-field for the related divider, these outputs have also individual enable bits (PLLPEN, PLLQEN, PLLREN). If this enable bit is not set, given PLL output does not provide the expected clock, even if the rest of PLL is set up correctly.
While this sounds quite logical, sometimes it may be source of surprising malfunction. For example, this post reports, that Cube does not set the respective PLL output enable bit, if this PLL output is used as source for MCO output without being used as clock of any other module.