Most peripherals in STM32 are attached to what's called an Advanced Peripheral Bus (APB), and work at whatever clock this bus works. There may be one or several (usually two) such buses in an STM32, and their clock is derived from the AHB bus to which it is attached (and clock of that is ultimately derived from the system clock).
As there may be many peripherals "hanging" out of one such APB bus, which means that the bus is physically large/long, thus its maximum clock frequency is limited and possibly below the maximum system clock frequency. Where two buses are present, often there is a "shorter" and "faster" one, and a "longer" and "slower" one.
This means, that for higher-speed STM32 models (such as the 'F4/'F7/'H7/'G4), when system clock is run at maximum, the APB clock may be required to be divided down, by /2 or /4 or more. But also in other models, APB bus clock may be divided down, e.g. to reduce power consumption, if fast access to peripherals and fast clocking of the peripherals is not a requirement.
Most peripherals use the clock of APB bus, to which they are attached, as their working clock. However, with timers, this is different in probably all STM32 models - if the related APB clock is divided from AHB clock by /2 or more, the timer's core clock, i.e. the clock which is used as "internal clock" to the timer's prescaler/counter/input filters/deadtime generator etc., is 2x as fast as the APB clock (the register interface is still clocked at the APB clock, but that's rarely noticed by the user and in the vast majority of cases negligible).
The consequence of this is an often seen complaint, that the timer runs twice faster than expected.
In some STM32 models - e.g. the 'F446 - there's one more twist: while by default the behaviour is the same as described above, the user can switch on an extra feature (in said 'F446 by setting RCC_DKCFGR.TIMPRE), which allows to use 4x APB clock, should its divider be /4 and larger (and still 2x APB if the divider is /2).