Problem discussed in this message has been brought to my attention by D.Anderle.

ST introduced High-Resolution Timer (HRTIM) in the STM32F334, intended to provide features needed in advanced switch-mode power source and motor control applications. HRTIM is in fact a collection of several timers (in principle each similar to the "ordinary" timers in STM32), one master and several (5) slaves, together with a complex web of signals and circuits. It also features output granularity finer than the timer's clock period, based on a delay line.

In newer STM32, HRTIM has been implemented in higher-end 'G4 and 'H7 families; althoug in 'H7 without the delay-line provided features.

In both the master and slave timers in HRTIM, there is a limitation on the Compare register, in that it cannot be set below 3 periods of the f_HRTIM clock. The particular lowest value which can be written into the Compare registers depend on CKPSC register, as in all HRTIM timing registers' N = (5-CKPSC) lowermost bits are used to steer the delay-line, and only bits higher than N control the "conventional" f_HRTIM-synchronous logic. For details, see Period and Compare registers min and max values table and the narrative around it; and description of HRTIM_MCMPyR and HRTIM_CMPyxR registers.

As a consequence, it is not possible in the simplest setup to set 0% (or even very low) PWM output duty cycles. One of the possible workarounds to set 0% output duty cycle is to set the given pin to GPIO output.

The same limitation applies also to the Period registers, but that usually does not have such surprising and limiting consequence.