As in many STM32 models representing the higher-end of a given family, STM32G0Bx/'G0Cx has its relatively large FLASH (up to 512kB) split into two banks (except in models marked to have only 128kB of FLASH).

The Prefetch failure when branching across flash memory banks erratum, pertinent to both rev.A and rev.Z of the chip, effectively restricts the two banks' usage to:

• either what's essentially just data in one of the banks (including cases where both banks contain code but not run simultaneously, e.g. when two versions of the code are stored in the two banks and selected upon startup);
• or forbids jumps between banks when prefetch is on, which is very clumsy to devise, and may decrease effective execution speed significantly.

User berendi put up a couple of relevant questions, answers to which may make both banks usable for code with certain cludges (such as trampolines in RAM), but ST did not comment.