Many STM32 families allow to select ADC's kernel clock to be asynchronous with its APB clock, e.g. being sourced from a different PLL output than the system/AHB/APB clock. This is often selected by ADC_CFGR2.CKMODE bitfield being set to ADCCLK, generated at product level, for which the source clock is selected in RCC, e.g. in RCC_CCIPR.ADCSEL bitfield.

Asynchronous kernel clock, besides introducing jitter in sampling (due to triggers and ADC kernel clock being asynchronous to each other), involve also resynchronization thus delays of signals passing between the ADC kernel and rest of the mcu. One potentially surprising consequence of such delay is the increased chance of invoking a second, "false" interrupt after a regular one.

Such "false" interrupt occurs, because the vast majority of interrupts in STM32 are level-triggered, and it takes time until a cleared interrupt source flag gets propagated from the peripheral to NVIC. Here, this propagation time is increased by the need for resynchronizing the interrupt signal coming from the ADC kernel with the APB/AHB clock system.