STM32 gotchas
216. ADC sampling causes "dip" in the input signal, and this may cause problems if this signal has other purposes, too

One ADC cycle consists of two phases: first, the sampling phase, when a sampling capacitor is charged from the input signal; and then the conversion phase, where the sampling capacitor is disconnected from input and its charge is distributed in successive steps into other capacitors, while comparing its voltage to the VREF+ reference 1.

So, at the beginning of the sampling phase, the input signal is switched to the sampling capacitor, which from previous conversions is charged to a generally unspecified voltage (anywhere between VREF- = VSS and VREF+). While the sampling capacitor is relatively small (around 6-8pF, depending on particular STM32 model), the switch is fast, and together with the input signal's source impedance this creates a "dip" (or "spike") in the input signal voltage. If the samping time is long enough, the sampling capacitor will eventually charge/discharge up to the input signal's voltage before conversion commences, so for the given conversion this "dip" is harmless.

However, this is not the case anymore - and the dip will cause problems - if the same signal is used also for other purposes, such us:

In these cases, the ADC input and the other analog input cannot be fed directly from the same primary signal source (i.e. they cannot be directly connected to each other). Instead, the input source has to be "split" into two separate and relatively low-impedance sources, e.g. by using two amplifiers in voltage follower configuration.

1. Details of this process are outlined in AN2834.