EFTON - STM32 gotchas

217.Incorrect ADC readout - because VREF+ impedance matters

Analog functions such as ADC and DAC use an external reference connected to the VREF+ pin ¹ ² ³. The current consumption from this pin, while relatively small, is not negligible, and - especially in case of ADC - has a pulsed character ⁴. That means, that the power supply connected to VREF+ has to be not only stable and noise-free, but also that source - and all involved PCB tracks or other connections - have to have as small impedance as possible.

Proper decoupling is also part of the power source impedance, in its high-frequency range. User SBeno.1 posted a series of waveforms illustrating what happens if decoupling is neglected. The outward effect was, that ADC exhibited a large number of missing codes.

Improperly chosen series resistance and/or RF choke (ferrite bead, etc.) can have detrimental effect on the analog performance, as experienced e.g. by user JLemi. This case also illustrates, that as VREF+ is shared between analog functions, loading it by one function (DAC) impacts the performance of other function (ADC).

The latter effect applies also to several ADCs, and for example in 'G4, the on-chip VREF+ impedance limits simultaneous operation of two and more ADCs as compared to operating only one ADC. Details of this can be found both in the ADC-related data in the DS, in AN5346, and also in this thread.

1. Strictly speaking, ADC and DAC work out of the voltage difference between VREF+ and VREF- pins. However, in most packages but the largets, VREF- is internally connected to VSSA. In packages where VREF- is present, there are relatively stringent requirements for the voltage difference between VREF- and VSSA (usually max. a few tens of mV). The requirement for low impedance path applies to VREF-, too, where available.

2. In smaller packages, VREF+ pin is internally connected to VDDA. The requirement for low impedance power source for this "merged" pin remains.

3. In some newer STM32 families - and in packages, where VREF+ pin is not bonded together with VDDA - VREF+ can be switched to an internal reference source, VREFBUF.

4. The ADC is of capacitive SAR type, and its operation involves connecting successively the internal capacitances to VREF+, which involves charge transfers (hence current pulses) to/from these capacitors. Similarly to the input signal loaded by the sampling capacitor, here too these pulses have to settle within the given time slot - here the clock period of ADC - otherwise they influence precision of the conversion.