STM32 gotchas
35.'F1 don't have the GPIO AF matrix

The STM32F1xx was the first STM32 family, conceived more than a decade ago. It immediately hit a sweet spot on the mcu market with the combination of features, peripherals, became very successful and is still popular today despite its age and shorcomings. Of course, unavoidably, errors were made, as witnessed by the relatively lengthy errata; but that's nothing extraodrinary given the immense complexity of the design.

One of the early decisions was to have a relatively fixed mapping of peripherals' inputs/outputs to physical pins. While developers would welcome the flexibility of a full matrix, this is a relatively expensive choice, given the silicon area such matrix and the interconnections web1 would occupy is not insignificant.

As it would be unreasonable to produce a separate chip for each package variant of one model, the same chip is packaged to different packages, with simply not bringing out some of the pins2. However, there are more peripherals than would fit onto pins on the least‑pin‑count packages, so there are several peripheral IO mapped onto the same physical pin in some cases. Normally, user should not enable (by setting its clock in RCC) more than one peripheral at a time, where such sharing occurs.

To increase flexibility, ST allows to "remap" some of the peripherals to pins available in the higher‑pin‑count packages. From the programmer's perspective, a separate peripheral, AFIO, serves this purpose; before writing to its registers its own clock has to be enabled in RCC.

In all newer STM32 models, the arrangement is different and there are several peripherals' inputs/outputs assigned to most of the pins. Once the developer sets a given pin to Alternative Function (AF) mode, he/she then has to choose, which particular peripheral's IO to connect to. This mapping is presented in the Datasheet, in a simple sparse matrix form. While this is still not a full matrix at all3 and there are shortcomings of this method4, too; the AF/pin assignment in those families is generally a simpler and cleaner process.

This difference might come as an unpleasant surprise for developers who are already familiar with other STM32 families, and then are asked to work with the 'F1.

1. Extensive interconnections might also require extra metallization layers, thus masks, all resulting in increase in both non‑recurring and per‑device cost.

2. In STM32, the individual ports are deliberately designed so, that the "higher" ports are available only in the higher pin count packages. For example, STM32F103x8/xB in 48‑pin package (i.e. 'F103C8/CB) has only GPIOA and GPIOB available; in 64‑pin ('F103R8/RB) it has also GPIOC; and in 100‑pin ('F103V8/VB) GPIOD and GPIOE become available. There are exemptions to this rule - the oscillator pins (for both HSE and LSE) are on fixed port pins, so those are available in all packages where the oscillator(s) is(are) available.

3. Only the most common peripherals such as timers and UART/I2C/SPI have pins mapped to multiple pins, the complex peripherals have usually a fixed mapping. This has to be borne in mind when designing in the STM32 into a circuit.

4. There are several, but let's pick the one which relates to 'F1: In 'F1 in some cases, two peripherals' inputs are/can be mapped onto one pin, and this may be useful. For example, where both a TIM channel and UART Rx can be mapped onto one pin, the timer with appropriate setting can automatically measure inactivity and throw an interrupt upon long inactivity (this is more flexible than the usual IDLE implementation in UART).