In STM32 - except STM32F1xx - peripheral IOs are assigned to physical pins through a simple setup process in GPIO: Once the developer sets a given pin to Alternative Function (AF) mode in respective GPIOx_MODER register bits, he/she then has to choose, which particular peripheral's IO to connect to, by setting respective bits in the GPIOx_AFR[x] register pair (sometimes marked also as AFRL/AFRH).

The value to be written into GPIOx_AFR[] is given in the Datasheet of each particular STM32 model, as a table titled STM32xxxx alternate function mapping. It is a sparse matrix, describing, which AF number corresponds to required peripheral, for each physical pin. The AF number is given by the column in which the given peripheral IO is written; column headers describe the set of peripherals to which the given AF is assigned.

This scheme has been introduced in the 'L1 model, where the AF number uniquely determines the peripheral. For example, wherever there is a TIM2 IO assigned to a pin, in these families, it's invariably AF1; all USART2 pins are AF7, etc.

This user-friendly scheme (even with the same assignment of AF numbers to individual peripherals) has been brought over to 'F2/'F4/'F7 models, with a few exceptions mainly for SPI/I2S.

Unfortunately, that was it, and in the rest of STM32 families the AF assignment to pins is more less random. Thus users who don't rely on tools generating automatically code (e.g. from CubeMX) have to check in the DS for each individual pin, which AF number corresponds to the required functionality.