STM32 gotchas
45.Not only frequency but also VOS setting implies FLASH waitstates

The first STM32 - the 'F1 family - were built using a 180nm CMOS technology, some 15 years ago. Since then, newer STM32 models are produced using even tighter silicon process - through 90nm down to 45nm - which makes the incredible level of integration found in these devices possible.

The voltages used commonly in board-level interconnects are relatively high, around 3V, to avoid issues with signal integrity at usual levels of noise. So these are also supply voltages commonly used at todays digital electronics, including the STM32. However, the tiny MOSFET transistors utilizing the shortest gate length (thus smallest dimensions) allowed by the mentioned technology nodes, would break down or have excessive leakage at those voltages, so most STM32 digital circuitry runs internally at lower supply voltage, 1.2 to 1.8V, some even lower, depending on particular model and technology used.

To achieve this "core" voltage while avoiding the extra burden of having one more power supply, most STM32 contain an internal LDO regulator, which drops the supply voltage from 1.8V-3.3V to the required core voltage. As the LDO means some energy loss, for the ultra-power-sensitive applications, some newer STM32 models have a variant with internal LDO switched off, core voltage to be supplied externally; and yet another models have variants with a built-in swithing-mode regulator (SMPS, requiring external inductor). But these are the exception, we won't discuss them here.

Many (perhaps most) STM32 allow the user to select one of several output voltages of the LDO. This allows a tradeoff between speed and consumption: lower LDO voltage means lower core voltage thus lower consumption, but also lower maximum clock frequency. There are usually two or three settings, and they are set by one or two bits in PWR module, usually called VOS.

The core voltage influences not only the logic circuitry, but the FLASH memory's speed depends on it. As FLASH is usually slower than the core logic, waitstates have to be inserted into each read, the number of waitstates has to be set by the user as appropriate.

So, when determining the required number of waitstates, besides system clock frequency, the VOS setting has to be also taken into mind. Details differ between particular STM32 families, so Reference Manual and sometimes also Datasheet for given model have to be consulted.