Timers, besides having the counting unit (prescaler and counter) and the control harness, they have several Capture-Compare channels. These don't have the ability to count, yet they represent most of the inputs and outputs of the timer (besides external clock inputs and "emergency" break inputs), which usually also connect to the actual pins (through the GPIO matrix). They also input/generate (through the control harness, or sometimes even directly) the internal signals going from/to other peripherals within the chip.
In STM32 timers, there's a varying amount of channels in various timers (1 to 6, 4 channels being the "gold standard"). The channels also have somewhat varying capabilities in different timers - good example of this are the complementary output and break features of channels in Advanced Timers. Mostly, timers with the same number have similar capabilities and similar number of channels across all STM32 families, but exceptions do exist.
However, even channels within one timer are not equal when it comes to their capabilities. Here is an incomplete list:
- only CH1 can generate TRGO from Input Capture (with the entirely incorrectly named Compare Pulse setting of TIMx_CR2.MMS)
- only CH1 and CH2 can be used as input to the slave-mode controller, and only CH1 with both edges (i.e. when the edge detector is to be used)
- as a consequence of previous item, only CH1 and CH2 can be used as inputs for encoder mode
- inputs in input capture mode can be "crossed" only between CH1/CH2 and CH3/CH4 couples
- in newer STM32 where some timers feature Asymmetric and Combined modes on output, only CH1/CH2 and CH3/CH4 pairs are coupled for this feature (in newer STM32 models' (e.g. 'G4) Advanced timers, CH5 can be combined with CH1/CH2/CH3, too - this still omits CH6 and CH4 from the mix)
- where available, the XOR function combines specifically CH1+CH2+CH3 and inputs to CH1
- in Advanced Timers, CH4 does not have complementary output, nor the BREAK logic (only CH1, CH2, CH3 have these)
- where available, CH5 and CH6 have restricted usability:
- they don't connect to pins through GPIO
- they can't generate TRGO
- even if they do generate corresponding flags as TIMx_SR.CCIF, they can't generate interrupts nor DMA requests
- as they came to be as an afterthought and ST rightly sticks to compatibility of registers layout within a peripheral, the CCRx for CH5 and CH6 are not continuous with other CCRx, which makes updating them through the TIMx_DCR/DMAR mechanism tricky