As the SPI module underwent significant changes across various STM32 families, the following information may not be relevant to the particular model you use.
In the SPI module, BSY flag is supposed to signal the period, while the SPI module transmits or receives data. Users often rely on this signal when generating framing signals, e.g. NSS for slaves, and are also often disappointed by the exact behaviour. ST does not document the exact timing of BSY signal for various settings properly.
What follows is anectdotal evidence, that generally, BSY is not suitable for the purpose it is intended for.
Users start transmission by writing data to the SPI_DR register. The general expectation is, that as soon as data are written, BSY goes active. When writing transmission routine for a single frame so that immediately after writing to SPI_DR a loop waits until BSY goes inactive, users are unpleasantly surprised to find out that the program exits the loop immediately (example here). The reason is, that after writing SPI_DR it takes some undocumented time until the frame gets transferred from the holding to the shift register, and BSY gets active only after that.
On the other end of transmission, when last bit of the last frame gets transmitted, at least in case of CPOL=0 and CPHA=0, on an STM32F407, BSY was seen to get inactive early, before the last SCK clock1:
If NSS signal towards a slave is derived from BSY, the slave may be aborted before the last frame is completed, thus slave may not receive that last frame at all.
One way to work around these problems in SPI transmitter, and avoid using BSY as a signal from which framing is derived, is to use the receiver's RXNE signal instead. This is working also in case when MISO pin is not assigned in the GPIO matrix; however, its timing (which again is not something properly documented by ST) might not be suitable in all CPOL/CPHA combinations.s
Using BSY in slave mode also has its share of issues, see for example the BSY bit may stay high at the end of data transfer in slave mode erratum in many STM32 models' errata sheet.
1. This "early BSY end" actually is displayed in waveform drawings, e.g. in RM0090 rev.17 Figure 253. TXE/RXNE/BSY behavior in Master / full-duplex mode (BIDIMODE=0 and RXONLY=0) in case of continuous transfers and some subsequent figures; however, the description does not mention it.