EFTON - STM32 gotchas

69.In 'F746/756, ADC triggering from TIM does not work properly

The ADC design in STM32 allows conversion to be started (triggered) from one of the timers, to allow regular ADC conversions. However, in the STM32F746, under certain APB bus/timer clock setting combinations, this triggering does not work.

The STM32F746/756 is ST's first implementation of the Cortex-M7 core, and as such it probably had seen a rushed development, as witnessed by a significant number of errata. Perhaps the the most annoying of them is Debugger keeps jumping into interrupt when single stepping, although to be fair, that comes directly from ARM. Nonetheless, this TIM-ADC error is just another in the list, which may make some users to consider other, newer members of the 'F7 family where these problems have been already fixed, or an entirely different family.

What is maybe even more surprising than the triggering bug itself is, that for some of the triggering sources there is a workaround in that after enabling the apparently unrelated DAC clock in RCC, triggering ADC from TIM starts to work.

While this issue is properly documented in the Missed ADC triggers from TIM1/TIM8, TIM2/TIM5/TIM4/TIM6/TRGO or TGRO2 event erratum, it is nevertheless surprising, as witnessed by repeated threads on the forum dealing whith this problem, e.g. here, here, here and here.

Example in Cube - and the fact that "step 3" is after "step 4" and the DAC clock enable - may hint, that a vital part of the workaround is to enable the DAC clock before starting the timer. This is not described by the erratum, but then some of the workarounds in errata are known to be not working, or perhaps work only under undescribed circumstances (such as particular sequencing, as may be the case here).