STM32 gotchas
75.Unexpected ETH interrupts after longer uptime (due to MAC management counters interrupts being enabled by default)

The ETH module is rather complex, and among other things it contains a set of counters counting good and bad frames in each direction. This sub-module is called MAC management counters (MMC). These registers serve to debug/benchmark the ETH communication in a given setup. Besides the counters themselves there is also a set of registers enabling interrupt, when a respective counter reaches half its count (i.e. 2^31).

Now the first confusing thing is, that these registers disable (in Synopsys's and ARM's lingo, "mask") given interrupts when their respective bits are set.

And by reset default these registers are cleared, so the related interrupts are enabled. This is again confusing, as in all other modules all interrupts are disabled by default.

It's also not that obvious during usual debugging that these interrupts are enabled - they kick in only after a prolonged time, as at least 2^31 frames has to be exchanged.

( On STM32 Forum, user Piranha provided a description of the variants of the problem for several families, and proposed respective fixes).