STM32 gotchas
89.How to set TRGO in TIM16/TIM17? Also, TIM channel needs output enabled if controls another module, e.g. ADC.

Many timers in STM32 have a mechanism through which they can output a signal (called TRGO, Trigger Output) towards other modules within the chip. This is then used for the inter-timer synchronization, but also in triggering ADC and DAC.

There are several sources from which TRGO can be chosen (in TIMx_CR2.MMS): Reset, Enable and Update, which are internal signals of the timer and its slave-mode controller; outputs of all 4 channels' output comparator (OCxREF); signal which sets channel 1 interrupt flag (regardless of whether CH1 is set as Capture or Compare - this signal is notoriously incorrectly called Compare Pulse throughout ST's materials and software).

However, in some STM32 models, other timers or modules such as ADC are triggered from timers (typically TIM16/TIM17), which don't have the TRGO setting facility (i.e. don't have the TIMx_CR2.MMS field, or don't have TIMx_CR2 register at all). How is TRGO generated in those timers?

Here, the signal output from timer instead of TRGO is identical to the signal driving the respective pin of such timer's (usually single) output channel. It is not merely OCxREF of given channel, but it includes also the enable signalling, i.e. the respective TIMx_CCER.CCEx has to be set. And, in timers which do have TIMx_BDCR, also bits from this register, impacting the enabled state of given pin, are considered (MOE, OSSI, etc.).

In other words, the effective triggering signal is result of AND of the output level signal and the enable signal, going from given timer channel into the AF matrix of GPIO. There is no need for any pin to be assigned to given timer channel in GPIO, though.

This description applies to all instances where triggering comes directly from a timer's channel, rather than TRGO (e.g. when an ADC is triggered by TIMx_OCx).

Discussion of this issue with ST participation here.