STM32 gotchas
96.TCM don't support highest clock frequencies in 'H723/725

This issue has been brought up in this thread on ST forum.

The STM32H7 family brought us brutal raw computing power, expressed mostly in raw megahertzs of system clock, but also in a complex bus system, built around an extensive 64-bit AXI bus matrix. To support this computing power, the ARM Cortex-M7 core relies heavily upon L1 cache interfacing the AXI matrix to the processor.

This setup of course brings also hard-to-control variations in details of program execution timing and resulting jitter in outwards signals. This in the vast majority of applications is negligible, thanks to both the high computing power and powerful peripherals hardware, which can handle many signals without need for immediate processor intervention.

However, as a legacy feature, the Cortex-M7 core supports also tightly-coupled memories (TCM), which allow better-controlled code execution than executing the caches/AXI system. TCM memories usually support zero wait state access.

The STM32H723/725 subfamily feature the highest system clock frequency amongst all STM32, up to 550Hz. However, as it turns out, the 'H723/725 don't support ECC for TCM at frequencies above 520MHz.

This information is conveyed indirectly: according to datasheet, frequencies above 520MHz require to have an innocently-sounding CPU_FREQ_BOOST option bit to be set. This bit is not explained in DS itself, and only RM clarifies that this bit switches off the TCMs' ECC.

As the 45nm technology used for the 'H7 family apparently requires ECC to guarantee data integrity in RAM, TCM is practically unusable above 520 MHz in that family.