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glossary
- Clone
- exact copy of the standard ( bible-described) device maybe with some internal program memory
- Derivative
- a chip with everything the standard ( bible-described) device has as default. That e.g. a port can be configured differently does not make it a deviate.
- Deviate
- a chip with most of what the standard ( bible-described) device has. The SILabs f3xx series is an example.
- SFR
- Special Function Register. 8-bit register needed for function of the core (e.g. accumulator, PSW) and for accessing the peripherals. Located at direct addresses 80h-FFh. See inside and SW model.
- DATA
- In program model, directly-accessible internal RAM (addresses 00-7F) - accessed e.g. with MOV data,xxx
- IDATA
- In program model, indirectly-accessible internal RAM (in 8051 addresses 00-7F, in 8052 addresses 00-FF), accessed e.g. with MOV @Rn. DATA is a subset of IDATA. The stack is located in IDATA (except on some derivatives, where the stack can extend into internal-XDATA). See also IRAM.
- XDATA
- In program model indirectly-accessible memory with MOVX (usually external RAM or ROM). If such is available, it refers also to a RAM (in excess of IRAM) integrated on chip, again accessed by MOVX. See also XRAM.
- PDATA
- rarely used expression for a 256-byte "page" of XDATA accessed by MOVX @Rn
- CODE
- Memory (usually ROM (FLASH)) accessed by instruction fetches, also indirectly-accessible with MOVC.
- EEPROM
- nonvolatile electrically erasable memory, byte-wise erasable and programmable. In some '51 derivatives integrated on-chip, accessed via associated SFRs. Can be used for storing constants or infrequently changing variables, as the erasing and programming is relatively lenghty (~ms).
- IRAM
- Physical term - RAM which is part of the '51 and/or '52 core, accessed as IDATA (see above).
- XRAM
- Physical term - Expanded indirectly-accessible memory. This type of memory is accessed via MOVX instructions (see XDATA). It may be realized as external RAM/ROM as well as integrated on chip.
- FPGA
- Field Programmable Gate Array - logic device, exact function of which depend on a setup. Typically they consist of relatively small cells implementing basic logic functions (a couple of gates and a flip-flop or so) interconnected together; the setup then selects which function of the cell is active and how it interconnects to other cells. Another type of programmable logic is CPLD (Complex Programmable Logic Device) which are usually of smaller logic density and don't implement too much sequential logic (flip-flops). CPLD originate in PAL/GAL (Programmable/Gate Array Logic) devices, they are formed by a large and-or array ending in so called macrocells (containing the flip-flop).
- ASIC
- Application Specific Integrated Circuit - custom made IC, often with a technology, which enables to convert it from FPGA (usually only defining one or two last metal layers - gate array or sea of gates)
- IAP
- In-Application? Programming - ability of a flash '51 to program its own flash from the running user application
- ISP: In-Situ? Programming - ability to program the flash '51 from an external host via some few-lines serial line (SPI, UART, JTAG). Strictly speaking, one can in-situ program also using parallel programming, but as it ears up most of the chips pins, it is highly inconvenient (read
- nobody does it this way)
- ICP
- In-Circuit? Programming - Philips' attempt to make the picture even less clear, by introducing an abbeviation that can be messed up with the previous two so easily. Refers to ISP using SPI in the LPC9xx family (ISP then refers to UART-ISP, some of the LPC9xx are capable of both).
- hex, intelhex, hexfile
- A file format for storing the "burnable" code - see the description. The name comes from "hexadecimal".