Various STM32 (sub)families utilize different methods to enter the built-in bootloader upon reset. The traditional method employed in the primeval STM32F1xx is to have a defined level on two pins: BOOT0 at logic 1 and BOOT1 at logic 0. Reason for using two pins instead of one is, that there are three kinds of memory which can be mapped at address 0 from where the Cortex-Mx processor actually boots: the user FLASH, the "system memory" (piece of FLASH programmed at factory and not user-reprogrammable), and RAM.

The gotcha lies in the fact, that while BOOT0 is a dedicated pin, BOOT1 is a GPIO (PB2). If user is unaware of the requirement of BOOT1 being at a certain level, results may be surprising, ranging from incongruent "randomly" unreliable bootloader entry, through a consistent but mysterious pattern e.g. "works at first powerup but not with pushbutton reset" all the way to entirely "unoperational" bootloader.

In particular, if there is enough parasitic capacitance on PB2/BOOT1 to "hold" its state reliably for some time, then when being powered up after a longer off period the pin is at logic 0 allowing relatively reliable bootloader entry. However, if it has been reset for whatever reason (soft-reset deliberately invoked to enter bootloader, pushbutton reset, rapid powerdown/up) while the pin was held at logic 1 being set as GPIO output, the parasitic capacitance will hold the level at logic 1 long enough to prevent bootloader entry. This is a very confusing behaviour.

ST used this original scheme (called Pattern 1 in AN2606) also in subsequent STM32 families, up until 'F4. In the newer 'F4 models ST started to combine the pins with option bits, and since the 'F0/'F3 era, BOOT1 is not used anymore, being entirely replaced by option bits.