STM32 gotchas
STM32 timeline and peripherals changes

We concentrate on the "general purpose" STM32, omitting 'WB/'WL (wireless).
We don't treat 'L4+ as a separate sub-family here, as it shares most characteristics with 'L4.

The original idea was to fill out the table with various modules' versions. However, this is a very hard task, and honestly, it should be ST doing it.

STM32 Family Introduced Perk Cortex max clock FLASH GPIO DMA BKPSRAM SPI USB
F1 2007 First M3 72 MHz no ECC APB single-port
ORed requests
device
(except OTG FS
in 'F105/107)
L1 2009
NRND 2023
Low‑power
Mid‑end
M3 32 MHz erased at 0x00
has EEPROM with ECC
AHB single-port
ORed requests
device
F2 2010 Hi‑end M3 M3 120 MHz no ECC, has OTP AHB 2x dual-port
channel select
4kB OTG FS+OTG HS
F4 2011 Hi‑end M4 M4 180 MHz no ECC, has OTP AHB 2x dual-port
channel select
4kB OTG FS+OTG HS
F0 2012 Low‑end M0 48 MHz no ECC AHB single-port device
F3 2012 Analog/ Mixed M4 72 MHz no ECC AHB single-port
ORed requests
device
L0 2013 Low‑power
Low‑end
M0+ 32 MHz erased at 0x00
has ECC, has EEPROM
IOPORT single-port device
F7 2014 Hi‑end M7 M7 216 MHz no ECC, has OTP AHB 2x dual-port
channel select
4kB OTG FS+OTG HS
(HS PHY 'F723)
L4 2015 Low‑power
Hi‑end
M4 80 MHz has ECC, has OTP AHB single-port OTG FS
H7 2016 Hi‑end M7(+M4) M7(+M4)480 MHz has ECC AHB4 4x(mixed)
DMAMUX
4kB OTG FS+OTG HS
G0 2018 Low‑end M0+ 64 MHz has ECC, has OTP IOPORT single-port
DMAMUX
device+host, but
only in 'G0Bx/0C1
G4 2019 Analog/ Mixed M4 170 MHz has ECC, has OTP AHB single-port
DMAMUX
device
L5 2019 Low‑power
Secure Mid‑end
M33 110 MHz has ECC, has OTP, AHB 2x single-port
DMAMUX
device
U5 2021 Low‑power
Secure Hi‑end
M33 160 MHz has ECC, has OTP AHB GPDMA+LPDMA OTG_FS
C0 2023 Lowest‑end M0+ 48 MHz no ECC, has OTP IOPORT single-port
(3ch only)
DMAMUX
---
H5 2023 Secure Hi‑end M33 250 MHz OTG_FS

For FLASH variants across families discussed here.

GPIO on AHB is faster, but GPIO on APB in 'F1 allows bit-banding.
IOPORT is a dedicated port on the Cortex-M0+ processor, allowing faster access from processor to GPIO at the cost of preventing DMA from accessing it.
In 'H7, GPIO is on a secondary bus-matrix, removed from processor and DMAs (except BDMA) through two busmatrices and respective bridges, making "manual toggling" of GPIO surprisingly slow.

The single-port DMA is described in AN2548, dual-port DMA in AN4031.
The DMA column also indicates, how requests from peripherals are steered to DMA: the simplest approach is that requests from several peripherals to an individual DMA channel are simply ORed together; in more advanced models there is a request-selecting multiplexer controlled by bits in DMA registers; and in the newest models there is a standalone DMAMUX unit, effectively implementing a full matrix between requests from various peripherals and the set of available DMA channels (plus some additional features).
In 'H7, there's one advanced MDMA on the AXIM bus matrix, two dual-port DMA and one single-port DMA (as BDMA).
In 'U5, the DMAs are very different from rest of the STM32. As far as requests go, GPDMA and LPDMA both contain an embedded unit similar to DMAMUX. GPDMA is dual-port, LPDMA is single-port.


Folowing infographics from 2017 (i.e. 'G0/'G4 missing) linked from community.st.com: STM32 timeline