FMC (Flexible memory controller) is the parallel memory interface in the STM32 world. It started under the moniker FSMC (Flexible static memory controller) in the initial 'F1 family. It was designed to handle
- conventional SRAM/pSRAM/EPROM with plain parallel address and data bus and nOE/nWE/nCS style of control, with optional external waitstate input;
- memories with multiplexed address/data buses in the "x51-style", with dedicated bus for upper part of address, where lower part of adderss is output onto data bus together with an address-latch signal, ahead of the actual data cycle;
- synchronous memories, which work in bursts and where lower part of address is generated by a counter from clock signal
- NAND FLASH (which in fact are a special case of synchronous memory), with poorly documented hardware ECC
FSMC supports several memories to be connected simultaneously, and as it requires a large number of pins, it is fully supported only on the larger-pin-count devices - the major limitation is, that lowermost address pins are not present in below and including 100-pin packages. The 100-pin package still contains enough FSMC pins to drive multiplexed-address memories, which includes conventional parallel-SRAM with a single parallel external latch. 100-pin package also allows to have a parallel data bus with the usual SRAM control for devices which require limited addressing, found often in TFT-LCD controllers, which usually require only one address line - ST (ab)uses this fact in marketing FSMC to have a dedicated "LCD-mode".
FSMC in this form was used also in the newer 'F2 family and the first models of 'F4 family ('F405/'F407). However, in the next "power" model of the 'F4 family, the 'F427/'F429, ST introduced an extension of the FSMC module, to support synchronous dynamic RAMs (SDRAMs). These have not only synchronous interface with a relatively complex signal multiplexing and timing, but they also require periodic refresh - and the hardware is expected to handle all this seamlessly for the user to experience plain reads and writes from the system (processor, DMAs, LCD controller (L) point of view.
To honor the fact that FSMC is no longer supports only static memories but also dynamic memories, "static" thus letter S was omitted from the name, confusingly undermining the common expectation, that more letters in module naming means more capabilities. The different naming is reflected also in naming of structs and symbols of course makes also porting or writing universal libraries unnecessary harder.
To cause even more confusion, ST mixes and matches the naming and features very freely, so that capabilites can't be inferred from the name and careful reading of the manuals is needed. For example, in the higher-end-'L4 and 'L4+ manuals, as well as in 'G4 manual, the module is called FSMC in the headlines (and indeed it does not support SDRAMs), but then in the first sentences of FSMC chapter, the following sentence appears:
This memory controller is also named flexible memory controller (FMC).
and subsequently the rest of manual consistently uses the moniker FMC, including naming of registers (and that also in the CMSIS-mandated device header). However, in the various selectors, 'L4/'L4+ appear in the group having FMC (together with those STM32 which do have genuine FMC with SDRAM support) while 'G4 appears in the same selectors as having FSMC.At the end of the day, FMC/FSMC is a surprisingly complex piece of hardware, which is relatively poorly described in the manuals with plenty of handwaving when it comes to details; featuring quite a couple of errata; and having minor but for some applications important differences between individual incarnations in individual (sub)families. While there's only one FMC/FSMC module per STM32, and there are not so many projects using it, so the problem with naming is perhaps a bit less annnoying than that of UART/USART and maybe could be called minor; FMC/FSMC is still a confusion and a completely unnecessary addition to all the complexities of that module.