STM32 gotchas
181. On the Commutation event (COM) in some timers

Timers, which have channels with complementary output - TIM1, TIM8, TIM20 called collectively Advanced Timers, and TIM15, TIM16, TIM17 - have an option to have the individual channels' enable bits (CCxE, CCxNE) in TIMx_CCER and the output-compare-mode bitfield (OCxM) in TIMx_CCMRx, preloaded1. This option is by default off and is switched on by setting TIMx_CR2.CCPC bit.

However, unlike other registers in timers which are preloaded, the "intermediate" values for these bits/bitfields (i.e. those directly written and being read back by the processor or any other busmaster) are not loaded into the "working" registers upon Update event. Rather, there is a dedicated event for loading these bits/bitfields, called Commutation event (COM). Remarkably, this event is there only for this sole purpose of loading preloaded enable bits and mode bitfields, intended to change them simultaneously at the same time for every channel of a timer.

Commutation event can be generated in two ways: in any case it can be generated "manually", by setting TIMx_EGR.COMG; but if TIMx_CR2.CCUS is set, commutation event is generated also upon rising edge of the TRGI signal.

1. This is not the only feature not directly related to complementary channels, shared by this group of timers - for example, they all also have the repetition counter.