In STM32, most peripherals need to have clock enabled in some of the RCC_AxBxENRx registers. However, sometimes it's not easy to spot the bit which enables some particular peripheral.
One of the reasons for this is, that sometimes a clock enable bit is common for several peripherals. This sometimes leads also to confusingly named enable bit.
Here are some examples:
- DMAMUX in some models is enabled together with DMA (or one of the DMAs) it serves
- a very common combo is SYSCFG with the "minor analog" modules, such as
- RCC_AxBxENRx.SYSCFGEN enabling SYSCFG + COMP + VREFBUF in 'L4 and 'G0
- RCC_AxBxENRx.SYSCFGEN enabling SYSCFG + COMP + VREFBUF + OPAMP in 'G4 (note that 'L4 does have a separate RCC_APB1ENR1.OPAMPEN bit)
- RCC_AxBxENRx.SYSCFGCOMPEN enabling SYSCFG + COMP in 'F0
- RCC_AxBxENRx.DCMIEN in 'L4+ enables either DCMI or PSSI, depending on the enable bit within the respective module (PSSI_CR.ENABLE bit and the DCMI_CR.ENABLE bit must not be set to 1 at the same time)
- in 'F4 (and possibly other models with dual bxCAN), CAN1 and CAN2 share the 512 byte (filter) memory, so in effect CAN2 can't work without CAN1 clock being enabled, even if CAN1 is not used
- in 'G4, RCC_AxBxENRx.ADC12EN enables both ADC1 + ADC2, and RCC_AxBxENRx.ADC345EN enables ADC3 + ADC4 + ADC5. While ADC1/ADC2 and ADC3/ADC4 form pairs tied together with a common portion of hardware (enabling to operate in dual mode), ADC5 is independent, so it's surprising that it is enabled together with ADC3/ADC4.
- In 'F4 (and probably also 'F2 and 'F7), there's a triple ADC (ADC1/ADC2/ADC3) with a common portion, which allows to use combined modes. The common portion is used also to set up the kernel clock, which is common to all 3 ADCs. The common portion also has bits to enable the temperature sensor/VBAT/VREFINT inputs, although they are connected only to ADC1. While all 3 ADCs do have separate enable bits, the common portion does not have a separate enable bit, and enabling either of the ADCs enables also the common portion (btw. this detail is not documented by ST)1,2.
1. Most peripherals in RCC have, besides an enable bit, also a reset bit, usually in the same position in RCC_AxBxRSTRx as is the respective enable bit in RCC_AxBxENRx. ADC1/ADC2/ADC3 in 'F4 is an exception in this, too, as they have only a single common reset bit, RCC_AxBxRSTRx.ADCRST, positioned where RCC_AxBxENRx.ADC1EN is.
2. As an interesting although useless detail, enabling either ADCx clock enables all 3 ADC registers for read, but only the enabled ADCx registers for write (see also footnote 1 here)