STM32 gotchas
187. Where's that clock enable? It's tied to some other peripheral.

In STM32, most peripherals need to have clock enabled in some of the RCC_AxBxENRx registers. However, sometimes it's not easy to spot the bit which enables some particular peripheral.

One of the reasons for this is, that sometimes a clock enable bit is common for several peripherals. This sometimes leads also to confusingly named enable bit.

Here are some examples:

1. Most peripherals in RCC have, besides an enable bit, also a reset bit, usually in the same position in RCC_AxBxRSTRx as is the respective enable bit in RCC_AxBxENRx. ADC1/ADC2/ADC3 in 'F4 is an exception in this, too, as they have only a single common reset bit, RCC_AxBxRSTRx.ADCRST, positioned where RCC_AxBxENRx.ADC1EN is.

2. As an interesting although useless detail, enabling either ADCx clock enables all 3 ADC registers for read, but only the enabled ADCx registers for write (see also footnote 1 here)