However, two different schemes are employed in SMT32 families to enable DMAMUX clock:
- In 'G4, 'L4+, 'L5 families, there is a dedicated DMAMUX enable bit, DMAMUX1EN1.
- In 'G0/'C0 and in 'H72, there is no separate DMAMUX bit. DMAMUX is enabled together by enabling DMA unit. In case where there are two DMA units (e.g. 'G0Bx), enabling either of the DMA units enables also DMAMUX.
The lesser-used low-power-clock bits in RCC are arranged similarly; and so are the reset bits, too: in STM32 families where DMAMUX is enabled together with DMA, it is also reset together with DMA; in families with separate DMAMUX clock enable bit there is also a separate DMAMUX reset bit in RCC.
These differences may lead to unpleasant surprises, when migrating between STM32 families.
1. With the exception of 'H7 (see footnote 2), there is always only one DMAMUX unit. Even if there are two DMA units in some models, the single DMAMUX unit serves both. Confusingly, ST uses an inconsistent naming of that single DMAMUX unit, calling it DMAMUX1 at some places and just DMAMUX at others, even if referring to that one particular instance.
2. In 'H7, there are three DMA units served by two DMAMUX units (the fourth MDMA does not have requests routed through a DMAMUX).
The reason lies in the complex bus system - DMAMUX1 serves DMA1 and DMA2 in the "not the highest speed, mostly peripherals" D2 domain,
and DMAMUX2 serves BDMA in the relatively separate low-power D4 domain.
(Again, ST is not very meticulous in adding the respective number to "DMAMUX" even when referring to particular one of the two units,
so documentation has to be read with care.)
DMAMUX2 is enabled together with BDMA. The 'H7 manual (RM0433 Rev 8) does not document how to enable DMAMUX1 clock; most likely it's enabled together with either of DMA1 or DMA2, similarly to 'G0Bx.