EFTON - STM32 gotchas

210. ADC at low sampling rate needs LFTRIG bit set, in 'G0/'C0/'U0/'U5

ADC in some STM32 families ('L4/'L5/'G4) have "wrong result after 1ms delay" erratum. There's probably some capacitive structure in the ADC, which gets parasitically charged/discharged through transistors leaks while the ADC sits idle for some (relatively) longer time, and influences adversely the ADC precision.

Apparently related to this problem, in some other, newer¹ STM32 families ('G0/'C0/'U0/'U5), a feature has been added to ADC to circumvent this issue. This feature is enabled by setting ADC_CFGR2.LFTRIG bit, and, from the programmer's standpoint, it causes extra ADC clock cycle to be added to the conversion.

While the original problem exhibited itself after >1ms of ADC being idle, ADC_CFGR2.LFTRIG requires to be set if the ADC is idle for more than 100μs.

1.Strangely, 'L5 and 'G4 are actually newer families than 'G0, yet they still don't have this feature and do have the erratum. Even newer families such as 'H5 don't have LFTRIG nor the erratum, so the underlying problem with ADC may have been fixed in some way in them.