In some cases, pacing (rate) of ADC readouts is given only by sampling time and conversion time itself, and is pushed by users to maximum. In such cases the only viable ADC result readout method is DMA.

However, DMA in itself is no magic, and DMA transfers take certain number of cycles, increased by potential conflicts on the buses. There is also some latency between DMA request generation (here: ADC end-of-conversion signal) and start of the DMA transfer, especially if DMAMUX is involved; this latency is also dependent on other DMA transfers in the same DMA controller.¹

So, as witnessed by user Utyf, even when using DMA, sometimes ADC cannot be pushed to its absolute limits, otherwise DMA may not be able to collect all data, resulting in ADC overrun and data collection stop. This state can be potentially detected by using the ADC overrun interrupt, but at that point, a portion of data is probably already lost.