The STM32L4P5 and STM32L4R5 (together with their crypto-enabled counterparts, 'L4Q5 and 'L4S5, respecitvely; and a couple of yet-higher-end models) form part of what ST calls STM32L4+ series. These form the pinnacle of the 'L4 family: L4+ is a low-power sub-family based around Cortex-M4F processor, with lots of memory, a bunch of powerful periferals and in high-pin-count packages.

Historically, 'L4R5 was the first model in this sub-family, with 'L4P5 coming somewhat later. It may appear - and it in many respect indeed is so - that STM32L4P5 was created as a stripped-down version, to cater for some particular client, who requested a model without the probably large GFXMMU unit (but with an extra SDMMC2), as those appear to be the only differences at the first glance.

There is also AN5017, which is not a direct migration between these two models but could be used to compare them - barring differences in RAM size and peripherals which are present/absent in one of the subfamilies, they otherwise appear to be pin and peripheral-address compatible.

However, there are subtle differences between the two, which in some cases prevents them to be entirely binary compatible, even if the "extra" peripherals are not used:

• As noticed by user mahapusha, the DMAMUX input channel numbering is shifted by 1 for almost all table, just because ADC2 has been *inserted* to position 6 in the 'L4P5. Would it be placed at the end of the table, instead, the binary compatibility would be perfect in this regard.
• The two models use a different version of RTC: the 'L4R5 uses RTCv2 while 'L4P5 uses RTCv3.

It's a pity ST does not pay more attention to strict compatibility between models within a family or subfamily, making replacement and sourcing chips more challenging than it would necessarily be ¹.