STM32 gotchas
205.In 'L4P5, TAMPER clears SRAM2

This is one of the issues which is not documented by ST, only found by observation.

TAMPER input is an important security feature of the battery-backup (VBAT) power domain. It is intimately related to RTC and the backup registers. In STM32 models which have RTCv3, backup registers together with some related setup registers have been separated from RTC to a semi-independent TAMP module.

The basic functionality of TAMPER is, that upon pulling some of the RTC_TAMPx input pin to active level, a timestamp is made in RTC, and the backup registers are erased. Most aspects of this functionality are configurable; details depend on the particular STM32 family.

As user frosticles reported, in STM32L4P5 - a member of the 'L4+ family - when TAMPER is activated, SRAM2 gets erased to all 0x00. This functionality is not documented in the associated RM/DS. And it of course may result in surprising crashes, if an unaware user places data or stack into SRAM2.

This security functionality is implemented in the 'L5 family, which is a successor to the 'L4+ family and shares much of its peripherals and general setup; except it is built around the newer Cortex-M33 processor, which is touted for its security features (in contrast to the older Cortex-M4 used in 'L4+). Maybe developers have already implemented this feature in 'L4P5 and then neglected to document it.